`timescale 1ns / 1ps

module adder_32_tb(
    );
    reg clk;
    reg rst;
    reg [31:0] in1;
    reg [31:0] in2;
    wire [31:0] out;
    
    adder_32 adder_32_0(.clk(clk),.rst(rst),.in1(in1),.in2(in2),.out(out));
    
    initial begin   
        clk=0;
        forever begin
            #20 clk=~clk;
        end 
    end
    initial begin
        rst=1;
        #20
        rst=0;
        #20
        in1=32'd1;
        in2=32'd2;
        #40
        in1=32'd100;
        in2=-32'd99;
        #40
        in1=32'd5;
        in2=-32'd20;
        #40
        in1=32'hf0000000;
        in2=-32'he0000000;
        #100 $finish;
    end
    
endmodule
